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data sheet ics853s057agi revision a may 16, 2012 1 ?2012 integrated device technology, inc. 4:1, differential-to-3.3v, 2.5v lvpecl/ecl clock data multiplexer ICS853S057I general description the ICS853S057I is a 4:1 different ial-to-3.3v or 2.5v lvpecl/ecl clock/data multiplexer which can operate up to 3ghz. the ICS853S057I has 4 differential selectable clock input pairs. the clk, nclk input pairs can acc ept lvpecl, lvds, cml or sstl levels. the fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. the multiplexer select control inputs have ecl/lvpecl interface levels. the select pins have internal pulldown resistors. features ? high speed 4:1 differential muliplexer ? one differential 3.3v, 2.5v lvpecl/ecl output ? four differential clkx, nclkx input pairs ? differential clkx, nclkx pairs can accept the following interface levels: lvpecl, lvds, cml, sstl ? maximum input/output frequency: 3ghz ? additive phase jitter, rms @ 622.08mhz: 0.073ps (typical) ? part-to-part skew: 250ps (maximum) ? propagation delay: 615ps (maximum) ? lvpecl mode operating voltage supply range: v cc = 2.375v to 3.465v, v ee = 0v ? ecl mode operating voltage supply range: v cc = 0v, v ee = -3.465v to -2.375v ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) packages 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nclk3 clk3 nclk2 clk2 nclk1 clk1 nclk0 clk0 v cc v ee v cc sel1 sel0 v cc q nq v cc v bb1 v bb2 v ee pin assignment ICS853S057I 20-lead tssop 6.5mm x 4.4mm x 0.925mm package body g package top view block diagram q nq clk0 nclk0 clk1 nclk1 0 0 0 1 1 0 1 1 sel0 v bb1 v bb2 sel1 clk2 nclk2 clk3 nclk3 pulldown pulldown pulldown pulldown pulldown pulldown pulldown pulldown pulldown pulldown (default)
ICS853S057I data sheet 4:1, differential-to-3 .3v, 2.5v lvpecl/ecl clock data multiplexer ics853s057agi revision a may 16, 2012 2 ?2012 integrated device technology, inc. table 1. pin descriptions note: pulldown refers to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics function tables table 3. control input function table number name type description 1, 14, 17, 20 v cc power positive supply pins. 2 clk0 input pulldown non-inverting differential clock input. 3 nclk0 input pulldown inverting differential clock input. 4 clk1 input pulldown non-inverting differential clock input. 5 nclk1 input pulldown inverting differential clock input. 6 clk2 input pulldown non-inverting differential clock input. 7 nclk2 input pulldown inverting differential clock input. 8 clk3 input pulldown non-inverting differential clock input. 9 nclk3 input pulldown inverting differential clock input. 10, 11 v ee power negative supply pins. 12, 13 v bb2, v bb1 output ecl reference outputs. 15, 16 nq, q output differe ntial output pair. ecl/l vpecl interface levels. 18, 19 sel0, sel1 input pulldown clock select inputs. ecl/lvpecl or lvcmos interface levels. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4 pf r pulldown input pulldown resistor 51 k ? control inputs clock out sel1 sel0 q, nq 0 0 (default) clk0, nclk0 01clk1, nclk1 10clk2, nclk2 11clk3, nclk3
ICS853S057I data sheet 4:1, differential-to-3 .3v, 2.5v lvpecl/ecl clock data multiplexer ics853s057agi revision a may 16, 2012 3 ?2012 integrated device technology, inc. absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v cc = 2.375v to 3.465v; v ee = 0v, t a = -40c to 85c table 4b. dc characteristics, v cc = 2.375v to 3.465v; v ee = 0v, t a = -40c to 85 c note 1: v il should not be less than -0.3v. note 2: common mode voltage is defined as v ih . table 4c. lvpecl dc characteristics, v cc = 2.375v to 3.465v; v ee = 0v, t a = -40c to 85 c note 1: outputs terminated with 50 ? to v cc ? 2v. item rating supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuous current surge current 50ma 100ma package thermal impedance, ja 87.2 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditions minimum typical maximum units v cc positive supply voltage 2.375 3.3 3.465 v i ee power supply current 25 ma symbol parameter test conditions minimum typical maximum units v pp input peak-to-peak voltage; note 1 0.15 1.3 v v cmr common mode range; note 1, 2 0.5 v cc ? 0.85 v i ih input high current clk[0:3], nclk[0:3] v cc = v in = 3.465v or 2.625v 150 a i il input low current clk[0:3], nclk[0:3] v cc = 3.465v or 2.625v, v in = 0v -10 a symbol parameter test conditions minimum typical maximum units v oh output high voltage; note 1 v cc ? 1.4 v cc ? 0.9 v v ol output low voltage; note 1 v cc ? 2.0 v cc ? 1.7 v v swing peak-to-peak output voltage swing 0.6 1.0 v
ICS853S057I data sheet 4:1, differential-to-3 .3v, 2.5v lvpecl/ecl clock data multiplexer ics853s057agi revision a may 16, 2012 4 ?2012 integrated device technology, inc. table 4d. ecl dc characteristics, v cc = 0v; v ee = 2.375v to 3.465v, t a = -40c to 85 c note 1: outputs terminated with 50 ? to v cc ? 2v. note 2: single-ended input operation is limited. v cc 3v in lvpecl mode. ac electrical characteristics table 5. ac characteristics, v cc = 2.375v to 3.465v; v ee = 0v or v cc = 0v; v ee = -3.8v to -2.375v,t a = -40c to 85c all parameters measured up to 1.5ghz, unless otherwise noted. note: electrical parameters are guaranteed over the specified ambi ent operating temperature range, which is established when th e device is mounted in a test socket with maintained trans verse airflow greater than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1: measured from the differential input crossi ng point to the differential output crossing point. note 2: defined as skew between outputs on different devices operating at the same supply voltage and with equal load condition s. using the same type of inputs on each device, the output s are measured at the differential cross points. note 3: this parameter is defined according with jedec standard 65. symbol parameter test conditio ns minimum typical maximum units v oh output high voltage; note 1 -1.125 -0.935 v v ol output low voltage; note 1 -1.895 -1.67 v v bb1, v bb2 output voltage reference; note 2 -1.3 v symbol parameter test conditions minimum typical maximum units f max output frequency 3ghz t jit additive phase jitter, rms; refer to additive phase jitter section 622.08mhz, 12khz ? 20mhz 0.073 ps t pd propagation delay; note 1 300 615 ps t sk(pp) part-to-part skew; note 2, 3 250 ps t r / t f output rise/fall time 20% to 80% 70 220 ps mux isolation mux isolation 622.08mhz, v in 1.6v to 2.4v -59 db
ICS853S057I data sheet 4:1, differential-to-3 .3v, 2.5v lvpecl/ecl clock data multiplexer ics853s057agi revision a may 16, 2012 5 ?2012 integrated device technology, inc. additive phase jitter the spectral purity in a band at a specific offset fr om the fundamental compared to the power of t he fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundament al frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specif ied, the phase noise is called a dbc value, which simply means dbm at a specif ied offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effect s on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specificat ions, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device m eets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. additive phase jitter @ 622.08mhz 12khz to 20mhz = 0.073ps (typical) ssb phase noise dbc/hz offset from carrier frequency (hz)
ICS853S057I data sheet 4:1, differential-to-3 .3v, 2.5v lvpecl/ecl clock data multiplexer ics853s057agi revision a may 16, 2012 6 ?2012 integrated device technology, inc. parameter measurement information lvpecl output load ac test circuit part-to-part skew propagation delay differential input level output rise/fall time scope qx nqx v ee v cc 2v -1.465v to -0.375v t sk(pp) part 1 part 2 nqx qx nqy qy t pd nclk[0:3] clk[0:3] nq q v cmr cross points v pp - v cc v ee nclkx clkx 20% 80% 80% 20% t r t f v swing nq q
ICS853S057I data sheet 4:1, differential-to-3 .3v, 2.5v lvpecl/ecl clock data multiplexer ics853s057agi revision a may 16, 2012 7 ?2012 integrated device technology, inc. application information wiring the differential input to accept single-ended levels figure 1 shows how the differential input can be wired to accept single-ended levels. the reference voltage v_ref = v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. fo r example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. figure 1. single-ended signal driving differential input recommendations for unused input pins inputs: clk/nclk inputs for applications not requiring the use of the differential input, a 1k ? resistor should be tied from nclk to v cc . single-ended lvpecl control pins all control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. v_ref single ended clock input v cc clkx nclkx r1 1k c1 0.1u r2 1k
ICS853S057I data sheet 4:1, differential-to-3 .3v, 2.5v lvpecl/ecl clock data multiplexer ics853s057agi revision a may 16, 2012 8 ?2012 integrated device technology, inc. clock input interface the clk/nclk accepts lvpecl, lvds, cml, sstl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 2a to2e show interface examples for the hiperclocks clk /nclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from anothe r vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 2a. hiperclocks clk/nclk input driven by a cml driver figure 2c. hiperclocks clk/nclk input driven by a 3.3v lvpecl driver figure 2e. hiperclocks clk/nclk input driven by an sstl driver figure 2b. hiperclocks clk/nclk input driven by a built-in pullup cml driver figure 2d. hiperclocks clk/nclk input driven by a 3.3v lvds driver clk nclk differential input cml 3.3v zo = 50 ? zo = 50 ? 3.3v 3.3v r1 50 r2 50 r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 ? zo = 50 ? clk nclk 3.3v 3.3v lvpecl differential input sstl 2.5v zo = 60 ? zo = 60 ? 2.5v r1 120 r2 120 r3 120 r4 120 clk nclk 3.3v differential input 3.3v r1 100 cml built-in pullup clk nclk 3.3v differential input zo = 50 ? zo = 50 ? 3.3v r1 100 lvds clk nclk 3.3v differential input zo = 50 ? zo = 50 ?
ICS853S057I data sheet 4:1, differential-to-3 .3v, 2.5v lvpecl/ecl clock data multiplexer ics853s057agi revision a may 16, 2012 9 ?2012 integrated device technology, inc. termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are lo w impedance follower outputs that generate ecl/lvpecl compatible out puts. therefore, terminating resistors (dc current pa th to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 3a and 3b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 3a. 3.3v lvpecl output termination figure 3b. 3.3v lvpecl output termination 3.3v v cc - 2v r1 50 ? r2 50 ? rtt z o = 50 ? z o = 50 ? + _ rtt = * z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v lvpecl input r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? lvpecl input 3.3v 3.3v + _
ICS853S057I data sheet 4:1, differential-to-3 .3v, 2.5v lvpecl/ecl clock data multiplexer ics853s057agi revision a may 16, 2012 10 ?2012 integrated device technology, inc. termination for 2.5v lvpecl outputs figure 4a and figure 4b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cc ? 2v. for v cc = 2.5v, the v cc ? 2v is very close to ground level. the r3 in figure 4b can be eliminated and the termination is shown in figure 4c. figure 4a. 2.5v lvpecl driver termination example figure 4c. 2.5v lvpecl driver termination example figure 4b. 2.5v lvpecl driver termination example 2.5v lvpecl driver v cc = 2.5v 2.5v 2.5v 50 ? 50 ? r1 250 ? r3 250 ? r2 62.5 ? r4 62.5 ? + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 ? 50 ? r1 50 ? r2 50 ? + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 ? 50 ? r1 50 ? r2 50 ? r3 18 ? + ?
ICS853S057I data sheet 4:1, differential-to-3 .3v, 2.5v lvpecl/ecl clock data multiplexer ics853s057agi revision a may 16, 2012 11 ?2012 integrated device technology, inc. power considerations this section provides information on power dissipa tion and junction temperature for the ics53s057i. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics53s057i is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v cc_max * i ee_max = 3.465v * 25ma = 86.625mw power (outputs) max = 31.1mw/loaded output pair total power_ max (3.3v, with all outputs switching) = 86.625mw + 31.1mw = 117.725mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 87.2c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.118w * 87.2c/w = 95.3c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ja for 20 lead tssop, forced convection ja by velocity meters per second 012.5 multi-layer pcb, jedec standard te st boards 87.2c/w 82.9c/w 80.7c/w
ICS853S057I data sheet 4:1, differential-to-3 .3v, 2.5v lvpecl/ecl clock data multiplexer ics853s057agi revision a may 16, 2012 12 ?2012 integrated device technology, inc. 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 5. figure 5. lvpecl driver circuit and termination t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cc ? 2v. for logic high, v out = v oh_max = v cc_max ? 0.935v (v cc_max ? v oh_max ) = 0.935v for logic low, v out = v ol_max = v cc_max ? 1.67v (v cc_max ? v ol_max ) = 1.67v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v oh_max ) = [(2v ? (v cc_max ? v oh_max ))/r l ] * (v cc_max ? v oh_max ) = [(2v ? 0.935v)/50 ? ] * 0.935v = 19.9mw pd_l = [(v ol_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v ol_max ) = [(2v ? (v cc_max ? v ol_max ))/r l] * (v cc_max ? v ol_max ) = [(2v ? 1.67v)/50 ? ] * 1.67v = 11.2mw total power dissipation per output pair = pd_h + pd_l = 31.1mw v out v cc v cc - 2v q1 rl 50
ICS853S057I data sheet 4:1, differential-to-3 .3v, 2.5v lvpecl/ecl clock data multiplexer ics853s057agi revision a may 16, 2012 13 ?2012 integrated device technology, inc. reliability information table 7. ja vs. air flow table for a 20 lead tssop transistor count the transistor count for ICS853S057I is: 251 package outline and package dimensions package outline - g suffix for 20 lead tssop table 8. package dimensions reference document: jedec publication 95, mo-153 ja by velocity meters per second 012.5 multi-layer pcb, jedec standard te st boards 87.2c/w 82.9c/w 80.7c/w all dimensions in millimeters symbol minimum maximum n 20 a 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 6.40 6.60 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10
ICS853S057I data sheet 4:1, differential-to-3 .3v, 2.5v lvpecl/ecl clock data multiplexer ics853s057agi revision a may 16, 2012 14 ?2012 integrated device technology, inc. ordering information table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 853s057agilf ics53s057ail ?lead-free? 20 lead tssop tube -40 c to 85 c 853s057agilft ics53s057ail ?lead-free? 20 lead tssop 2500 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, whic h would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications, su ch as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not aut horize or warrant any idt product for use in life support devices or critical medical instruments.
ICS853S057I data sheet 4:1, differential-to-3 .3v, 2.5v lvpecl/ecl clock data multiplexer ics853s057agi revision a may 16, 2012 15 ?2012 integrated device technology, inc. revision history sheet rev table page description of change date a t5 4 7 ac characteristics table - added thermal note. recommendations for unused input pins - modified clk/nclk input paragraph. changed datasheet header/footer. 7/30/09 a t1 2 pin description table - pins 18 and 19 (selx description) added lvcmos levels. 5/16/2012
ICS853S057I data sheet 4:1, differential-to-3 .3v, 2.5v lvpecl/ecl clock data multiplexer disclaimer integrated device technology, inc. (idt) and its subsid iaries reserve the right to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is subj ect to change without notice. performance specifications and the operating parameters of the de scribed products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merchantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property righ ts of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2012. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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